Add L432, L442. (#16016)
This commit is contained in:
parent
0f53e1333f
commit
77062e9a36
10 changed files with 358 additions and 2 deletions
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@ -502,6 +502,43 @@ ifneq ($(findstring STM32G474, $(MCU)),)
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STM32_BOOTLOADER_ADDRESS ?= 0x1FFF0000
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endif
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ifneq (,$(filter $(MCU),STM32L432 STM32L442))
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# Cortex version
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MCU = cortex-m4
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# ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
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ARMV = 7
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## chip/board settings
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# - the next two should match the directories in
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# <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
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MCU_FAMILY = STM32
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MCU_SERIES = STM32L4xx
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# Linker script to use
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# - it should exist either in <chibios>/os/common/startup/ARMCMx/compilers/GCC/ld/
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# or <keyboard_dir>/ld/
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MCU_LDSCRIPT ?= STM32L432xC
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# Startup code to use
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# - it should exist in <chibios>/os/common/startup/ARMCMx/compilers/GCC/mk/
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MCU_STARTUP ?= stm32l4xx
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# Board: it should exist either in <chibios>/os/hal/boards/,
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# <keyboard_dir>/boards/, or drivers/boards/
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BOARD ?= GENERIC_STM32_L432XC
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PLATFORM_NAME ?= platform_l432
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USE_FPU ?= yes
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# UF2 settings
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UF2_FAMILY ?= STM32L4
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# Bootloader address for STM32 DFU
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STM32_BOOTLOADER_ADDRESS ?= 0x1FFF0000
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endif
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ifneq (,$(filter $(MCU),STM32L433 STM32L443))
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# Cortex version
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MCU = cortex-m4
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@ -13,7 +13,7 @@
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},
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"processor": {
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"type": "string",
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"enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66FX1M0", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F405", "STM32F407", "STM32F411", "STM32F446", "STM32G431", "STM32G474", "STM32L412", "STM32L422", "STM32L433", "STM32L443", "GD32VF103", "WB32F3G71", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"]
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"enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66FX1M0", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F405", "STM32F407", "STM32F411", "STM32F446", "STM32G431", "STM32G474", "STM32L412", "STM32L422", "STM32L432", "STM32L433", "STM32L442", "STM32L443", "GD32VF103", "WB32F3G71", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"]
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},
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"audio": {
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"type": "object",
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@ -43,7 +43,9 @@ You can also use any ARM chip with USB that [ChibiOS](https://www.chibios.org) s
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* [STM32G474](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x4.html)
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* [STM32L412](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x2.html)
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* [STM32L422](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x2.html)
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* [STM32L432](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x2.html)
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* [STM32L433](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x3.html)
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* [STM32L442](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x2.html)
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* [STM32L443](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x3.html)
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### WestBerryTech (WB32)
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21
keyboards/handwired/onekey/nucleo_l432kc/config.h
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21
keyboards/handwired/onekey/nucleo_l432kc/config.h
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@ -0,0 +1,21 @@
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// Copyright 2021 Nick Brassel (@tzarc)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include "config_common.h"
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#define PRODUCT Onekey L432KC
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#define MATRIX_COL_PINS { A2 }
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#define MATRIX_ROW_PINS { A1 }
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#define UNUSED_PINS
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#define BACKLIGHT_PIN B8
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#define BACKLIGHT_PWM_DRIVER PWMD4
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#define BACKLIGHT_PWM_CHANNEL 3
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#define BACKLIGHT_PAL_MODE 2
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#define RGB_DI_PIN A0
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#define RGB_CI_PIN B13
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#define ADC_PIN A0
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5
keyboards/handwired/onekey/nucleo_l432kc/readme.md
Normal file
5
keyboards/handwired/onekey/nucleo_l432kc/readme.md
Normal file
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@ -0,0 +1,5 @@
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# STM32 Nucleo-L432 onekey
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To trigger keypress, short together pins *A1* and *A2*.
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You'll also need to connect `VIN`, `GND`, USB `D+` to `PA12`/`D2`, and USB `D-` to `PA11`/`D10`.
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5
keyboards/handwired/onekey/nucleo_l432kc/rules.mk
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5
keyboards/handwired/onekey/nucleo_l432kc/rules.mk
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@ -0,0 +1,5 @@
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# MCU name
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MCU = STM32L432
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# Bootloader selection
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BOOTLOADER = stm32-dfu
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@ -13,7 +13,7 @@ QMK_FIRMWARE_UPSTREAM = 'qmk/qmk_firmware'
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MAX_KEYBOARD_SUBFOLDERS = 5
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# Supported processor types
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CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK66FX1M0', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F405', 'STM32F407', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32L412', 'STM32L422', 'STM32L433', 'STM32L443', 'GD32VF103', 'WB32F3G71'
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CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK66FX1M0', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F405', 'STM32F407', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32L412', 'STM32L422', 'STM32L432', 'STM32L433', 'STM32L442', 'STM32L443', 'GD32VF103', 'WB32F3G71'
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LUFA_PROCESSORS = 'at90usb162', 'atmega16u2', 'atmega32u2', 'atmega16u4', 'atmega32u4', 'at90usb646', 'at90usb647', 'at90usb1286', 'at90usb1287', None
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VUSB_PROCESSORS = 'atmega32a', 'atmega328p', 'atmega328', 'attiny85'
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@ -0,0 +1,9 @@
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# List of all the board related files.
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c
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# Required include directories
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BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC
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# Shared variables
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ALLCSRC += $(BOARDSRC)
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ALLINC += $(BOARDINC)
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@ -0,0 +1,10 @@
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// Copyright 2021 Nick Brassel (@tzarc)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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// Fixup equivalent usages within QMK as the base board definitions only go up to high
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#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
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#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
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# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
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#endif
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267
platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h
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267
platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h
Normal file
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* STM32L4xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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#define STM32L4xx_MCUCONF
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#define STM32L432_MCUCONF
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#define STM32L433_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_VOS STM32_VOS_RANGE1
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_MSIPLL_ENABLED FALSE
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#define STM32_MSIRANGE STM32_MSIRANGE_4M
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#define STM32_MSISRANGE STM32_MSISRANGE_4M
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSI16
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#define STM32_PLLM_VALUE 1
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#define STM32_PLLN_VALUE 10
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#define STM32_PLLPDIV_VALUE 0
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#define STM32_PLLP_VALUE 7
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#define STM32_PLLQ_VALUE 2
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#define STM32_PLLR_VALUE 2
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV1
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_STOPWUCK STM32_STOPWUCK_MSI
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_MCOPRE STM32_MCOPRE_DIV1
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
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#define STM32_PLLSAI1N_VALUE 24
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#define STM32_PLLSAI1PDIV_VALUE 0
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#define STM32_PLLSAI1P_VALUE 7
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#define STM32_PLLSAI1Q_VALUE 2
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#define STM32_PLLSAI1R_VALUE 2
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/*
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* Peripherals clock sources.
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*/
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#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
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#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
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#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
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#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
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#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
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#define STM32_SAI1SEL STM32_SAI1SEL_OFF
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#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#define STM32_IRQ_EXTI1635_38_PRIORITY 6
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#define STM32_IRQ_EXTI18_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_EXTI20_PRIORITY 6
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#define STM32_IRQ_EXTI21_22_PRIORITY 15
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#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
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#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
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#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
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#define STM32_IRQ_TIM1_CC_PRIORITY 7
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#define STM32_IRQ_TIM2_PRIORITY 7
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#define STM32_IRQ_TIM6_PRIORITY 7
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#define STM32_IRQ_TIM7_PRIORITY 7
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#define STM32_IRQ_USART1_PRIORITY 12
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#define STM32_IRQ_USART2_PRIORITY 12
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#define STM32_IRQ_LPUART1_PRIORITY 12
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_COMPACT_SAMPLES FALSE
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
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/*
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* CAN driver system settings.
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*/
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#define STM32_CAN_USE_CAN1 FALSE
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#define STM32_CAN_CAN1_IRQ_PRIORITY 11
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_DUAL_MODE FALSE
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#define STM32_DAC_USE_DAC1_CH1 FALSE
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#define STM32_DAC_USE_DAC1_CH2 FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM6 FALSE
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#define STM32_GPT_USE_TIM7 FALSE
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#define STM32_GPT_USE_TIM15 FALSE
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#define STM32_GPT_USE_TIM16 FALSE
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM15 FALSE
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#define STM32_ICU_USE_TIM16 FALSE
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_ADVANCED FALSE
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM15 FALSE
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#define STM32_PWM_USE_TIM16 FALSE
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/*
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* RTC driver system settings.
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*/
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#define STM32_RTC_PRESA_VALUE 32
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#define STM32_RTC_PRESS_VALUE 1024
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#define STM32_RTC_CR_INIT 0
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#define STM32_RTC_TAMPCR_INIT 0
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 FALSE
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#define STM32_SERIAL_USE_LPUART1 FALSE
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#define STM32_SERIAL_USART1_PRIORITY 12
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#define STM32_SERIAL_USART2_PRIORITY 12
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#define STM32_SERIAL_LPUART1_PRIORITY 12
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY 8
|
||||
#define STM32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 FALSE
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 TRUE
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG FALSE
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 FALSE
|
||||
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
|
||||
|
||||
#endif /* MCUCONF_H */
|
Loading…
Reference in a new issue