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Add autorouting via GitHub Workflow (#8)

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Leo Batyuk 2021-12-10 22:16:00 +01:00 committed by GitHub
parent 8a4e3a3f54
commit 22780e497b
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79 changed files with 161 additions and 50369 deletions
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17
.github/actions/autoroute/action.yml vendored Normal file
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@ -0,0 +1,17 @@
name: 'Autoroute'
description: 'Autoroute a given DSN file to SES with FreeRouting'
inputs:
dsn_file:
description: 'Specctra DSN input file'
required: true
ses_file:
description: 'Specctra SES output file'
required: true
runs:
using: 'docker'
image: 'docker://soundmonster/freerouting_cli:v0.1.0'
entrypoint: '/bin/sh'
args:
- '-c'
- |
java -jar /opt/freerouting_cli.jar -de ${{ inputs.dsn_file }} -do ${{ inputs.ses_file }}

20
.github/actions/export-dsn/action.yml vendored Normal file
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name: 'Export DSN'
description: 'Export Specctra DSN from a Kicad PCB'
inputs:
pcb_file:
description: 'Kicad input file'
required: true
dsn_file:
description: 'Specctra DSN output file'
required: true
runs:
using: 'docker'
image: 'docker://soundmonster/kicad-automation-scripts:latest'
entrypoint: '/bin/sh'
args:
- '-c'
# GH actions set $HOME to a weird location and we have to move Kicad settings there first
- |
mkdir -p $HOME/.config/kicad ;
cp /root/.config/kicad/* $HOME/.config/kicad ;
/usr/lib/python2.7/dist-packages/kicad-automation/pcbnew_automation/export_dsn.py ${{ inputs.pcb_file }} ${{ inputs.dsn_file }}

24
.github/actions/export-gerbers/action.yml vendored Normal file
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name: 'Export Gerbers'
description: 'Export Gerber files from a Kicad PCB'
inputs:
pcb_file:
description: 'Kicad input file'
required: true
gerbers_dir:
description: 'Gerbers folder'
required: true
fab:
description: 'Fabrication profile'
default: 'jlcpcb'
flags:
description: 'Additional flags for kikit fab'
default: '--no-assembly'
runs:
using: 'docker'
image: 'docker://yaqwsx/kikit:v0.7'
entrypoint: '/bin/sh'
args:
- '-c'
- |
mkdir -p $GITHUB_WORKSPACE/${{ inputs.gerbers_dir }} ;
kikit fab ${{ inputs.fab }} ${{ inputs.flags }} $GITHUB_WORKSPACE/${{ inputs.pcb_file }} $GITHUB_WORKSPACE/${{ inputs.gerbers_dir }}

23
.github/actions/import-ses/action.yml vendored Normal file
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name: 'Import SES to Kicad'
description: 'Import Specctra SES into a Kicad PCB'
inputs:
pcb_input_file:
description: 'Kicad input file'
required: true
pcb_output_file:
description: 'Kicad output file'
required: true
ses_file:
description: 'Specctra SES file'
required: true
runs:
using: 'docker'
image: 'docker://soundmonster/kicad-automation-scripts:latest'
entrypoint: '/bin/sh'
args:
- '-c'
# GH actions set $HOME to a weird location and we have to move Kicad settings there first
- |
mkdir -p $HOME/.config/kicad ;
cp /root/.config/kicad/* $HOME/.config/kicad ;
/usr/lib/python2.7/dist-packages/kicad-automation/pcbnew_automation/import_ses.py $GITHUB_WORKSPACE/${{ inputs.pcb_input_file }} $GITHUB_WORKSPACE/${{ inputs.ses_file }} ;

54
.github/workflows/build.yml vendored Normal file
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on: [push, pull_request, workflow_dispatch]
name: Build
jobs:
generate:
runs-on: ubuntu-latest
name: Generate
steps:
- name: Checkout
uses: actions/checkout@v2
- name: Use Node.js 17
uses: actions/setup-node@v2
with:
node-version: 17.x
- name: Install dependencies
run: npm install
- name: Generate unrouted PCBs
run: npm run gen
- name: Export DSN for main PCB
uses: ./.github/actions/export-dsn
with:
pcb_file: output/pcbs/board.kicad_pcb
dsn_file: output/pcbs/board.dsn
- name: Autoroute main PCB
uses: ./.github/actions/autoroute
with:
dsn_file: output/pcbs/board.dsn
ses_file: output/pcbs/board.ses
- name: Import SES into main PCB
uses: ./.github/actions/import-ses
with:
pcb_input_file: output/pcbs/board.kicad_pcb
pcb_output_file: output/pcbs/board_routed.kicad_pcb
ses_file: output/pcbs/board.ses
- name: Export Gerbers for top plate
uses: ./.github/actions/export-gerbers
with:
pcb_file: output/pcbs/top_plate.kicad_pcb
gerbers_dir: output/gerbers/top_plate
- name: Export Gerbers for bottom plate
uses: ./.github/actions/export-gerbers
with:
pcb_file: output/pcbs/bottom_plate.kicad_pcb
gerbers_dir: output/gerbers/bottom_plate
- name: Export Gerbers for main PCB
uses: ./.github/actions/export-gerbers
with:
pcb_file: output/pcbs/board.kicad_pcb
gerbers_dir: output/gerbers/board
- name: Persist output
uses: actions/upload-artifact@v2
with:
name: samoklava-routed-pcbs-and-gerbers
path: output

5
Makefile
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@ -1,11 +1,14 @@
# .DELETE_ON_ERROR: # .DELETE_ON_ERROR:
.SECONDARY: .SECONDARY:
.PHONY: clean all .PHONY: clean all setup
.DEFAULT: all .DEFAULT: all
container_cmd ?= docker container_cmd ?= docker
container_args ?= -w /board -v $(shell pwd):/board --rm container_args ?= -w /board -v $(shell pwd):/board --rm
setup:
npm install
# outputs from # outputs from
output/pcbs/board.kicad_pcb output/pcbs/top_plate.kicad_pcb output/pcbs/bottom_plate.kicad_pcb &: samoklava.yaml output/pcbs/board.kicad_pcb output/pcbs/top_plate.kicad_pcb output/pcbs/bottom_plate.kicad_pcb &: samoklava.yaml
npm run gen npm run gen

20
README.md
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@ -16,4 +16,22 @@ The interesting thing about this keyboard is that it's a declarative design ("sa
* uses [kicad-automation-scripts](https://github.com/productize/kicad-automation-scripts) and [FreeRouting](https://github.com/freerouting/freerouting) to **automatically route the traces on the PCB** * uses [kicad-automation-scripts](https://github.com/productize/kicad-automation-scripts) and [FreeRouting](https://github.com/freerouting/freerouting) to **automatically route the traces on the PCB**
* uses [KiKit](https://github.com/yaqwsx/KiKit) to render PCB previews (see top of this file) and production-ready **Gerber files** * uses [KiKit](https://github.com/yaqwsx/KiKit) to render PCB previews (see top of this file) and production-ready **Gerber files**
See the [Makefile](Makefile) for more details. ## Features
* Extra pins and a slider switch for wireless Promicro clones (tested with nice!nano)
* Wired operation should be possible but is not tested; TRRS footprints are included and routed
* Reset switches are easily accessible
## How to
If you would like to modify this:
* fork it
* change `samoklava.yaml` to your liking
* push your changes; the build it GitHub Workflow will pick it up, autoroute and generate Gerbers, all in a zip file.
See https://github.com/soundmonster/samoklava/actions
* or:
* make sure to have Docker CLI and NodeJS installed
* run `make setup clean all`
* check the `output` folder for KiCad PCBs and Gerbers
See the [workflow](.github/workflows/build.yml) or the [Makefile](Makefile) for more details.

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403
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1859
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X117.62Y24.31
X117.62Y21.77
X117.62Y19.23
T5
X107.0Y13.45
X107.0Y6.95
T6
X120.0Y11.7
X120.0Y8.7
X120.0Y11.7
X120.0Y8.7
T7
X113.4Y-0.5
X120.4Y-0.5
X113.4Y-2.5
X120.4Y-2.5
T8
X66.5Y45.9
X77.5Y45.9
X30.5Y11.9
X41.5Y11.9
X66.5Y28.9
X77.5Y28.9
X12.5Y34.0
X23.5Y34.0
X48.5Y32.3
X59.5Y32.3
X77.581Y-7.995
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X66.5Y11.9
X77.5Y11.9
X48.5Y15.3
X59.5Y15.3
X113.46Y-25.423
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X12.5Y17.0
X23.5Y17.0
X12.5Y0.0
X23.5Y0.0
X84.5Y27.2
X95.5Y27.2
X30.5Y45.9
X41.5Y45.9
X84.5Y44.2
X95.5Y44.2
X96.668Y-14.348
X106.194Y-19.848
X48.5Y49.3
X59.5Y49.3
X84.5Y10.2
X95.5Y10.2
X30.5Y28.9
X41.5Y28.9
T9
X31.0Y15.65
X36.0Y17.85
X36.0Y17.85
X41.0Y15.65
X67.0Y32.65
X72.0Y34.85
X72.0Y34.85
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X18.0Y39.95
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X23.0Y37.75
X49.0Y36.05
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X90.0Y33.15
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X31.0Y49.65
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X90.0Y16.15
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T2
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126
output/gerbers/board/gerber/board.gbrjob
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31
output/gerbers/board/gerber/drill_report.rpt
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@ -1,31 +0,0 @@
Drill report for output/routed_pcbs/board.kicad_pcb
Created on Sat Nov 13 16:54:47 2021
Copper Layer Stackup:
=============================================================
L1 : F.Cu front
L2 : B.Cu back
Drill file 'board.drl' contains
plated through holes:
=============================================================
T1 0.40mm 0.016" (24 holes)
T2 0.90mm 0.035" (8 holes) (with 8 slots)
T3 0.99mm 0.039" (36 holes)
T4 1.09mm 0.043" (52 holes)
T5 1.30mm 0.051" (2 holes)
Total plated holes count 122
Not plated through holes are merged with plated holes
unplated through holes:
=============================================================
T6 0.90mm 0.035" (4 holes)
T7 1.20mm 0.047" (4 holes)
T8 1.70mm 0.067" (36 holes)
T9 3.00mm 0.118" (72 holes)
T10 3.43mm 0.135" (18 holes)
Total unplated holes count 134

BIN
output/gerbers/board/gerbers.zip
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114
output/gerbers/bottom_plate/gerber/bottom_plate-MaskBottom.gbr
View file

@ -1,114 +0,0 @@
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G04 #@! TF.CreationDate,2021-11-13T16:54:45+00:00*
G04 #@! TF.ProjectId,bottom_plate,626f7474-6f6d-45f7-906c-6174652e6b69,VERSION_HERE*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Soldermask,Bot*
G04 #@! TF.FilePolarity,Negative*
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114
output/gerbers/bottom_plate/gerber/bottom_plate-MaskTop.gbr
View file

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G04 #@! TF.CreationDate,2021-11-13T16:54:45+00:00*
G04 #@! TF.ProjectId,bottom_plate,626f7474-6f6d-45f7-906c-6174652e6b69,VERSION_HERE*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Soldermask,Top*
G04 #@! TF.FilePolarity,Negative*
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114
output/gerbers/bottom_plate/gerber/bottom_plate-PasteBottom.gbr
View file

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G04 #@! TF.CreationDate,2021-11-13T16:54:45+00:00*
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G04 #@! TF.FileFunction,Paste,Bot*
G04 #@! TF.FilePolarity,Positive*
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114
output/gerbers/bottom_plate/gerber/bottom_plate-PasteTop.gbr
View file

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114
output/gerbers/bottom_plate/gerber/bottom_plate-SilkBottom.gbr
View file

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114
output/gerbers/bottom_plate/gerber/bottom_plate-SilkTop.gbr
View file

@ -1,114 +0,0 @@
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125
output/gerbers/bottom_plate/gerber/bottom_plate.gbrjob
View file

@ -1,125 +0,0 @@
{
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21
output/gerbers/bottom_plate/gerber/drill_report.rpt
View file

@ -1,21 +0,0 @@
Drill report for output/routed_pcbs/bottom_plate.kicad_pcb
Created on Sat Nov 13 16:54:45 2021
Copper Layer Stackup:
=============================================================
L1 : F.Cu front
L2 : B.Cu back
Drill file 'bottom_plate.drl' contains
plated through holes:
=============================================================
Total plated holes count 0
Not plated through holes are merged with plated holes
unplated through holes:
=============================================================
Total unplated holes count 0

BIN
output/gerbers/bottom_plate/gerbers.zip
View file

Binary file not shown.

21
output/gerbers/top_plate/gerber/drill_report.rpt
View file

@ -1,21 +0,0 @@
Drill report for output/routed_pcbs/top_plate.kicad_pcb
Created on Sat Nov 13 16:54:27 2021
Copper Layer Stackup:
=============================================================
L1 : F.Cu front
L2 : B.Cu back
Drill file 'top_plate.drl' contains
plated through holes:
=============================================================
Total plated holes count 0
Not plated through holes are merged with plated holes
unplated through holes:
=============================================================
Total unplated holes count 0

251
output/gerbers/top_plate/gerber/top_plate-CmtUser.gbr
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output/gerbers/top_plate/gerber/top_plate-CuBottom.gbr
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252
output/gerbers/top_plate/gerber/top_plate-MaskTop.gbr
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252
output/gerbers/top_plate/gerber/top_plate-PasteBottom.gbr
View file

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252
output/gerbers/top_plate/gerber/top_plate-PasteTop.gbr
View file

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252
output/gerbers/top_plate/gerber/top_plate-SilkBottom.gbr
View file

@ -1,252 +0,0 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.1.5+dfsg1-2build2*
G04 #@! TF.CreationDate,2021-11-13T16:54:26+00:00*
G04 #@! TF.ProjectId,top_plate,746f705f-706c-4617-9465-2e6b69636164,VERSION_HERE*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Legend,Bot*
G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 5.1.5+dfsg1-2build2) date 2021-11-13 16:54:26*
%MOMM*%
%LPD*%
G04 APERTURE LIST*
G04 #@! TA.AperFunction,Profile*
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G04 #@! TD*
G04 APERTURE END LIST*
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252
output/gerbers/top_plate/gerber/top_plate-SilkTop.gbr
View file

@ -1,252 +0,0 @@
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G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
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(outline (path signal 150 3000 -1750 -3000 -1750))
(outline (path signal 150 -3000 -1750 -3000 -1500))
(outline (path signal 150 -3000 1500 -3000 1750))
(outline (path signal 150 -3000 1750 3000 1750))
(outline (path signal 150 3000 1750 3000 1500))
(outline (path signal 150 -3000 -1750 3000 -1750))
(outline (path signal 150 3000 -1750 3000 -1500))
(outline (path signal 150 -3000 -1750 -3000 -1500))
(outline (path signal 150 -3000 1750 -3000 1500))
(outline (path signal 150 -3000 1750 3000 1750))
(outline (path signal 150 3000 1750 3000 1500))
(pin Round[A]Pad_2000_um 2 -3250 0)
(pin Round[A]Pad_2000_um 1 3250 0)
)
(padstack Round[A]Pad_1000_um
(shape (circle F.Cu 1000))
(shape (circle B.Cu 1000))
(attach off)
)
(padstack Round[A]Pad_1752.6_um
(shape (circle F.Cu 1752.6))
(shape (circle B.Cu 1752.6))
(attach off)
)
(padstack Round[A]Pad_1905_um
(shape (circle F.Cu 1905))
(shape (circle B.Cu 1905))
(attach off)
)
(padstack Round[A]Pad_2000_um
(shape (circle F.Cu 2000))
(shape (circle B.Cu 2000))
(attach off)
)
(padstack Oval[A]Pad_1600x2200_um
(shape (path F.Cu 1600 0 -300 0 300))
(shape (path B.Cu 1600 0 -300 0 300))
(attach off)
)
(padstack RoundRect[A]Pad_1500x1500_376.427_um
(shape (polygon F.Cu 0 440.366 745.708 503.746 728.726 563.213 700.995 616.963 663.36
663.36 616.963 700.995 563.214 728.726 503.746 745.708 440.366
751.427 375 751.427 -375 745.708 -440.366 728.726 -503.746
700.995 -563.213 663.36 -616.963 616.963 -663.36 563.214 -700.995
503.746 -728.726 440.366 -745.708 375 -751.427 -375 -751.427
-440.366 -745.708 -503.746 -728.726 -563.213 -700.995 -616.963 -663.36
-663.36 -616.963 -700.995 -563.214 -728.726 -503.746 -745.708 -440.366
-751.427 -375 -751.427 375 -745.708 440.366 -728.726 503.746
-700.995 563.213 -663.36 616.963 -616.963 663.36 -563.214 700.995
-503.746 728.726 -440.366 745.708 -375 751.427 375 751.427
440.366 745.708))
(shape (polygon B.Cu 0 440.366 745.708 503.746 728.726 563.213 700.995 616.963 663.36
663.36 616.963 700.995 563.214 728.726 503.746 745.708 440.366
751.427 375 751.427 -375 745.708 -440.366 728.726 -503.746
700.995 -563.213 663.36 -616.963 616.963 -663.36 563.214 -700.995
503.746 -728.726 440.366 -745.708 375 -751.427 -375 -751.427
-440.366 -745.708 -503.746 -728.726 -563.213 -700.995 -616.963 -663.36
-663.36 -616.963 -700.995 -563.214 -728.726 -503.746 -745.708 -440.366
-751.427 -375 -751.427 375 -745.708 440.366 -728.726 503.746
-700.995 563.213 -663.36 616.963 -616.963 663.36 -563.214 700.995
-503.746 728.726 -440.366 745.708 -375 751.427 375 751.427
440.366 745.708))
(attach off)
)
(padstack Rect[B]Pad_2600x2600_um
(shape (rect B.Cu -1300 -1300 1300 1300))
(attach off)
)
(padstack Rect[B]Pad_635x1143_um
(shape (rect B.Cu -317.5 -571.5 317.5 571.5))
(attach off)
)
(padstack Rect[B]Pad_900x900_um
(shape (rect B.Cu -450 -450 450 450))
(attach off)
)
(padstack Rect[B]Pad_900x1200_um
(shape (rect B.Cu -450 -600 450 600))
(attach off)
)
(padstack Rect[B]Pad_900x1250_um
(shape (rect B.Cu -450 -625 450 625))
(attach off)
)
(padstack Rect[B]Pad_1500x1500_um
(shape (rect B.Cu -750 -750 750 750))
(attach off)
)
(padstack Rect[T]Pad_2600x2600_um
(shape (rect F.Cu -1300 -1300 1300 1300))
(attach off)
)
(padstack Rect[T]Pad_635x1143_um
(shape (rect F.Cu -317.5 -571.5 317.5 571.5))
(attach off)
)
(padstack Rect[T]Pad_900x900_um
(shape (rect F.Cu -450 -450 450 450))
(attach off)
)
(padstack Rect[T]Pad_900x1200_um
(shape (rect F.Cu -450 -600 450 600))
(attach off)
)
(padstack Rect[T]Pad_900x1250_um
(shape (rect F.Cu -450 -625 450 625))
(attach off)
)
(padstack Rect[T]Pad_1500x1500_um
(shape (rect F.Cu -750 -750 750 750))
(attach off)
)
(padstack Rect[A]Pad_1752.6x1752.6_um
(shape (rect F.Cu -876.3 -876.3 876.3 876.3))
(shape (rect B.Cu -876.3 -876.3 876.3 876.3))
(attach off)
)
(padstack Rect[A]Pad_1778x1778_um
(shape (rect F.Cu -889 -889 889 889))
(shape (rect B.Cu -889 -889 889 889))
(attach off)
)
(padstack "Via[0-1]_800:400_um"
(shape (circle F.Cu 800))
(shape (circle B.Cu 800))
(attach off)
)
)
(network
(net pinky_bottom
(pins S1-1 S1-1@1 D1-2 D1-2@1 D1-1@2)
)
(net P20
(pins S1-2 S1-2@1 S2-2 S2-2@1 S3-2 S3-2@1 MCU1-6 MCU2-6)
)
(net P6
(pins D1-1 D1-1@1 D1-2@2 D4-1 D4-1@1 D4-2@2 D7-1 D7-1@1 D7-2@2 D10-1 D10-1@1
D10-2@2 D13-1 D13-1@1 D13-2@2 MCU1-21 MCU2-21)
)
(net pinky_home
(pins S2-1 S2-1@1 D2-2 D2-2@1 D2-1@2)
)
(net P5
(pins D2-1 D2-1@1 D2-2@2 D5-1 D5-1@1 D5-2@2 D8-1 D8-1@1 D8-2@2 D11-1 D11-1@1
D11-2@2 D14-1 D14-1@1 D14-2@2 MCU1-20 MCU2-20)
)
(net pinky_top
(pins S3-1 S3-1@1 D3-2 D3-2@1 D3-1@2)
)
(net P4
(pins D3-1 D3-1@1 D3-2@2 D6-1 D6-1@1 D6-2@2 D9-1 D9-1@1 D9-2@2 D12-1 D12-1@1
D12-2@2 D15-1 D15-1@1 D15-2@2 MCU1-19 MCU2-19)
)
(net ring_bottom
(pins S4-1 S4-1@1 D4-2 D4-2@1 D4-1@2)
)
(net P19
(pins S4-2 S4-2@1 S5-2 S5-2@1 S6-2 S6-2@1 MCU1-7 MCU2-7)
)
(net ring_home
(pins S5-1 S5-1@1 D5-2 D5-2@1 D5-1@2)
)
(net ring_top
(pins S6-1 S6-1@1 D6-2 D6-2@1 D6-1@2)
)
(net middle_bottom
(pins S7-1 S7-1@1 D7-2 D7-2@1 D7-1@2)
)
(net P18
(pins S7-2 S7-2@1 S8-2 S8-2@1 S9-2 S9-2@1 S16-2 S16-2@1 MCU1-8 MCU2-8)
)
(net middle_home
(pins S8-1 S8-1@1 D8-2 D8-2@1 D8-1@2)
)
(net middle_top
(pins S9-1 S9-1@1 D9-2 D9-2@1 D9-1@2)
)
(net index_bottom
(pins S10-1 S10-1@1 D10-2 D10-2@1 D10-1@2)
)
(net P15
(pins S10-2 S10-2@1 S11-2 S11-2@1 S12-2 S12-2@1 S17-2 S17-2@1 MCU1-9 MCU2-9)
)
(net index_home
(pins S11-1 S11-1@1 D11-2 D11-2@1 D11-1@2)
)
(net index_top
(pins S12-1 S12-1@1 D12-2 D12-2@1 D12-1@2)
)
(net inner_bottom
(pins S13-1 S13-1@1 D13-2 D13-2@1 D13-1@2)
)
(net P14
(pins S13-2 S13-2@1 S14-2 S14-2@1 S15-2 S15-2@1 S18-2 S18-2@1 MCU1-10 MCU2-10)
)
(net inner_home
(pins S14-1 S14-1@1 D14-2 D14-2@1 D14-1@2)
)
(net inner_top
(pins S15-1 S15-1@1 D15-2 D15-2@1 D15-1@2)
)
(net near_thumb
(pins S16-1 S16-1@1 D16-2 D16-2@1 D16-1@2)
)
(net P7
(pins D16-1 D16-1@1 D16-2@2 D17-1 D17-1@1 D17-2@2 D18-1 D18-1@1 D18-2@2 MCU1-22
MCU2-22)
)
(net home_thumb
(pins S17-1 S17-1@1 D17-2 D17-2@1 D17-1@2)
)
(net far_thumb
(pins S18-1 S18-1@1 D18-2 D18-2@1 D18-1@2)
)
(net RAW
(pins MCU1-1 MCU2-1)
)
(net GND
(pins MCU1-2 MCU1-15 MCU1-16 MCU2-2 MCU2-15 MCU2-16 TRRS1-3 TRRS2-3 B1-2)
)
(net RST
(pins MCU1-3 MCU2-3 B1-1)
)
(net VCC
(pins MCU1-4 MCU2-4 TRRS1-2 TRRS2-2)
)
(net P21
(pins MCU1-5 MCU2-5)
)
(net P16
(pins MCU1-11 MCU2-11)
)
(net P10
(pins MCU1-12 MCU2-12)
)
(net P1
(pins MCU1-13 MCU2-13)
)
(net P0
(pins MCU1-14 MCU2-14 TRRS1-4 TRRS2-4)
)
(net P2
(pins MCU1-17 MCU2-17)
)
(net P3
(pins MCU1-18 MCU2-18)
)
(net P8
(pins MCU1-23 MCU2-23)
)
(net P9
(pins MCU1-24 MCU2-24)
)
(net Bplus
(pins MCU1-25 MCU2-25 J1-2 J2-2 T1-2 T2-2)
)
(net Bminus
(pins MCU1-25@1 MCU2-25@1 PAD2-1 PAD2-1@1)
)
(net Braw
(pins PAD1-1 PAD1-1@1 J1-1 J2-1 T1-1 T2-1)
)
(class kicad_default "" P0 P1 P10 P14 P15 P16 P18 P19 P2 P20 P21 P3 P4
P5 P6 P7 P8 P9 RST far_thumb home_thumb index_bottom index_home index_top
inner_bottom inner_home inner_top middle_bottom middle_home middle_top
near_thumb pinky_bottom pinky_home pinky_top ring_bottom ring_home ring_top
(circuit
(use_via Via[0-1]_800:400_um)
)
(rule
(width 250)
(clearance 200.1)
)
)
(class Power Bminus Bplus Braw GND RAW VCC
(circuit
(use_via Via[0-1]_800:400_um)
)
(rule
(width 500)
(clearance 200.1)
)
)
)
(wiring
)
)

2301
output/pcbs/board.kicad_pcb
View file

File diff suppressed because it is too large Load diff

33
output/pcbs/board.pro
View file

@ -1,33 +0,0 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

107
output/pcbs/bottom_plate.dsn
View file

@ -1,107 +0,0 @@
(pcb /board/output/pcbs/bottom_plate.dsn
(parser
(string_quote ")
(space_in_quoted_tokens on)
(host_cad "KiCad's Pcbnew")
(host_version "5.0.1-33cea8e~67~ubuntu18.04.1")
)
(resolution um 10)
(unit um)
(structure
(layer F.Cu
(type signal)
(property
(index 0)
)
)
(layer B.Cu
(type signal)
(property
(index 1)
)
)
(boundary
(path pcb 0 62517.6 58731.9 63000 58532.1 63414.2 58214.2 63732.1 57800
63931.9 57317.6 64000 56800 64000 55400 80000 55400 80560.5 55319.9
81076.1 55085.8 81505.4 54716.7 81814.1 54242 81977.4 53699.9
82000 53700 98000 53700 98589.4 53611.2 99126.5 53352.6 99563.5 52947.2
99861.6 52431.1 99994.4 51850 120000 51850 120518 51781.9
121000 51582.1 121414 51264.2 121732 50850 121932 50367.6
122000 49850 122000 -20208.7 129724 -28251.6 130042 -28665.8
130241 -29148.2 130310 -29665.8 130241 -30183.5 130042 -30665.8
129724 -31080.1 119117 -41686.7 118703 -42004.5 118221 -42204.3
117703 -42272.5 117185 -42204.3 116703 -42004.5 116289 -41686.7
72707.1 -16524.7 26000 -9500 10000 -9500 9482.36 -9431.85
9000 -9232.05 8585.79 -8914.21 8267.95 -8500 8068.15 -8017.64
8000 -7500 8000 41500 8068.15 42017.6 8267.95 42500 8585.79 42914.2
9000 43232.1 9482.36 43431.9 10000 43500 26000 43500 26000 53400
26068.1 53917.6 26267.9 54400 26585.8 54814.2 27000 55132.1
27482.4 55331.9 28000 55400 44000 55400 44000 56800 44068.1 57317.6
44267.9 57800 44585.8 58214.2 45000 58532.1 45482.4 58731.9
46000 58800 62000 58800 62517.6 58731.9)
)
(keepout "" (polygon signal 0 109947 -21341.9 109607 -21569.5 109379 -21910.1 109299 -22311.9
109379 -22713.8 109607 -23054.4 109947 -23282 110349 -23361.9
110751 -23282 111092 -23054.4 111319 -22713.8 111399 -22311.9
111319 -21910.1 111092 -21569.5 110751 -21341.9 110349 -21261.9
109947 -21341.9))
(keepout "" (polygon signal 0 71598.2 -5149.93 71257.5 -5377.54 71029.9 -5718.18
70950 -6120 71029.9 -6521.82 71257.5 -6862.46 71598.2 -7090.07
72000 -7170 72401.8 -7090.07 72742.5 -6862.46 72970.1 -6521.82
73050 -6120 72970.1 -5718.18 72742.5 -5377.54 72401.8 -5149.93
72000 -5070 71598.2 -5149.93))
(keepout "" (polygon signal 0 26598.2 970.074 26257.5 742.462 26029.9 401.818 25950 0
26029.9 -401.818 26257.5 -742.462 26598.2 -970.074 27000 -1050
27401.8 -970.074 27742.5 -742.462 27970.1 -401.818 28050 0
27970.1 401.818 27742.5 742.462 27401.8 970.074 27000 1050
26598.2 970.074))
(keepout "" (polygon signal 0 26598.2 29870.1 26257.5 29642.5 26029.9 29301.8 25950 28900
26029.9 28498.2 26257.5 28157.5 26598.2 27929.9 27000 27850
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27970.1 29301.8 27742.5 29642.5 27401.8 29870.1 27000 29950
26598.2 29870.1))
(keepout "" (polygon signal 0 80598.2 45170.1 80257.5 44942.5 80029.9 44601.8 79950 44200
80029.9 43798.2 80257.5 43457.5 80598.2 43229.9 81000 43150
81401.8 43229.9 81742.5 43457.5 81970.1 43798.2 82050 44200
81970.1 44601.8 81742.5 44942.5 81401.8 45170.1 81000 45250
80598.2 45170.1))
(via "Via[0-1]_800:400_um")
(rule
(width 250)
(clearance 200.1)
(clearance 200.1 (type default_smd))
(clearance 50 (type smd_smd))
)
)
(placement
)
(library
(padstack "Via[0-1]_800:400_um"
(shape (circle F.Cu 800))
(shape (circle B.Cu 800))
(attach off)
)
)
(network
(class kicad_default ""
(circuit
(use_via Via[0-1]_800:400_um)
)
(rule
(width 250)
(clearance 200.1)
)
)
(class Power
(circuit
(use_via Via[0-1]_800:400_um)
)
(rule
(width 500)
(clearance 200.1)
)
)
)
(wiring
)
)

154
output/pcbs/bottom_plate.kicad_pcb
View file

@ -1,154 +0,0 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
(title_block
(title KEYBOARD_NAME_HERE)
(rev VERSION_HERE)
(company YOUR_NAME_HERE)
)
(general
(thickness 1.6)
)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.05)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "")
)
(net_class Power "This is the power net class."
(clearance 0.2)
(trace_width 0.5)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
)
(gr_line (start 10 9.5) (end 26 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 8 7.5) (end 8 -41.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 10 7.5) (end 8 7.5) (angle -90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 26 -43.5) (end 10 -43.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 10 -41.5) (end 10 -43.5) (angle -90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 44 -55.4) (end 28 -55.4) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 28 -53.4) (end 28 -55.4) (angle -90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 26 -53.4) (end 26 -43.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 64 -55.4) (end 64 -56.8) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 62 -56.8) (end 64 -56.8) (angle -90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 62 -58.8) (end 46 -58.8) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 46 -56.8) (end 46 -58.8) (angle -90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 44 -56.8) (end 44 -55.4) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 80 -53.4) (end 81.9773914 -53.6998722) (angle -81.37677661279061) (layer Edge.Cuts) (width 0.15))
(gr_line (start 80 -55.4) (end 64 -55.4) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 98 -51.7) (end 99.9943671 -51.85) (angle -85.69877776512043) (layer Edge.Cuts) (width 0.15))
(gr_line (start 98 -53.7) (end 82 -53.7) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 82 -51.7) (end 82 -53.7) (angle -0.6477024783535228) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 117.7030442 40.2724513) (end 116.2888306 41.6866649) (angle -90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 119.1172578 41.6866649) (end 129.7238595 31.080063199999998) (angle 90) (layer Edge.Cuts) (width 0.15))
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33
output/pcbs/bottom_plate.pro
View file

@ -1,33 +0,0 @@
update=22/05/2015 07:44:53
version=1
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126
output/pcbs/top_plate.dsn
View file

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224
output/pcbs/top_plate.kicad_pcb
View file

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33
output/pcbs/top_plate.pro
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@ -1,33 +0,0 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

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(rev VERSION_HERE)
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29
output/routed_pcbs/bottom_plate.ses
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(session bottom_plate
(base_design bottom_plate)
(placement
(resolution um 10)
)
(was_is
)
(routes
(resolution um 10)
(parser
(host_cad "KiCad's Pcbnew")
(host_version "5.0.1-33cea8e~67~ubuntu18.04.1")
)
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(padstack "Via[0-1]_800:400_um"
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(circle F.Cu 8000 0 0)
)
(shape
(circle B.Cu 8000 0 0)
)
(attach off)
)
)
(network_out
)
)
)

222
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(gr_line (start 91.466508 4.469254) (end 77.943547 0.845788) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 77.943547 0.845788) (end 74.32008 14.368749) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 91.868716 19.659705) (end 103.993071 26.659705) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 103.993071 26.659705) (end 110.993071 14.535349) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 110.993071 14.535349) (end 98.868716 7.535349) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 98.868716 7.535349) (end 91.868716 19.659705) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 107.449996 29.312296) (end 117.349491 39.211791) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 117.349491 39.211791) (end 127.248986 29.312296) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 127.248986 29.312296) (end 117.349491 19.412801) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 117.349491 19.412801) (end 107.449996 29.312296) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_circle (center 27 -28.9) (end 28.05 -28.9) (layer Edge.Cuts) (width 0.15))
(gr_circle (center 27 0) (end 28.05 0) (layer Edge.Cuts) (width 0.15))
(gr_circle (center 81 -44.2) (end 82.05 -44.2) (layer Edge.Cuts) (width 0.15))
(gr_circle (center 72 6.12) (end 73.05 6.12) (layer Edge.Cuts) (width 0.15))
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)

29
output/routed_pcbs/top_plate.ses
View file

@ -1,29 +0,0 @@
(session top_plate
(base_design top_plate)
(placement
(resolution um 10)
)
(was_is
)
(routes
(resolution um 10)
(parser
(host_cad "KiCad's Pcbnew")
(host_version "5.0.1-33cea8e~67~ubuntu18.04.1")
)
(library_out
(padstack "Via[0-1]_800:400_um"
(shape
(circle F.Cu 8000 0 0)
)
(shape
(circle B.Cu 8000 0 0)
)
(attach off)
)
)
(network_out
)
)
)