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Kopimi illustrations

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This commit is contained in:
Cat /dev/Nulo 2022-04-01 23:43:28 -03:00
parent 2cd38c9c6d
commit 33f8f5b7c9
10 changed files with 7 additions and 30704 deletions
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2
.gitattributes vendored Normal file
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@ -0,0 +1,2 @@
*.kicad_pcb filter=lfs diff=lfs merge=lfs -text
*.zip filter=lfs diff=lfs merge=lfs -text

BIN
output/gerber.zip
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Binary file not shown.

27514
output/pcbs/board-routed.kicad_pcb
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75
output/pcbs/board-routed.kicad_prl
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@ -1,75 +0,0 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 1,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
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17,
18,
19,
20,
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33,
34,
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],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "board-routed.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

4
output/pcbs/board-routed.kicad_pro
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@ -127,7 +127,7 @@
"pinned_symbol_libs": []
},
"meta": {
"filename": "board.kicad_pro",
"filename": "board-routed.kicad_pro",
"version": 1
},
"net_settings": {
@ -184,7 +184,7 @@
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"netlist": "../../../../",
"specctra_dsn": "",
"step": "",
"vrml": ""

637
output/pcbs/board.dsn
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@ -1,637 +0,0 @@
(pcb /board/output/pcbs/board.dsn
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(pin Rect[B]Pad_900x900_um @4 3700 -1100)
(pin Rect[B]Pad_900x900_um @5 -3700 -1100)
(pin Rect[B]Pad_900x900_um @6 -3700 1100)
)
(image lib:bat
(pin RoundRect[A]Pad_1500x2250_376.427_um 1 -2000 0)
(pin RoundRect[A]Pad_1500x2250_376.427_um 1@1 0 0)
(pin RoundRect[A]Pad_1500x2250_376.427_um 1@2 2000 0)
)
(image kbd:ResetSW
(outline (path signal 150 3000 -1500 3000 -1750))
(outline (path signal 150 3000 -1750 -3000 -1750))
(outline (path signal 150 -3000 -1750 -3000 -1500))
(outline (path signal 150 -3000 1500 -3000 1750))
(outline (path signal 150 -3000 1750 3000 1750))
(outline (path signal 150 3000 1750 3000 1500))
(outline (path signal 150 -3000 -1750 3000 -1750))
(outline (path signal 150 3000 -1750 3000 -1500))
(outline (path signal 150 -3000 -1750 -3000 -1500))
(outline (path signal 150 -3000 1750 -3000 1500))
(outline (path signal 150 -3000 1750 3000 1750))
(outline (path signal 150 3000 1750 3000 1500))
(pin Round[A]Pad_2000_um 2 -3250 0)
(pin Round[A]Pad_2000_um 1 3250 0)
)
(padstack Round[A]Pad_1000_um
(shape (circle F.Cu 1000))
(shape (circle B.Cu 1000))
(attach off)
)
(padstack Round[A]Pad_1752.6_um
(shape (circle F.Cu 1752.6))
(shape (circle B.Cu 1752.6))
(attach off)
)
(padstack Round[A]Pad_2000_um
(shape (circle F.Cu 2000))
(shape (circle B.Cu 2000))
(attach off)
)
(padstack Round[A]Pad_2032_um
(shape (circle F.Cu 2032))
(shape (circle B.Cu 2032))
(attach off)
)
(padstack RoundRect[A]Pad_1500x2250_376.427_um
(shape (polygon F.Cu 0 440.366 1120.71 503.746 1103.73 563.213 1075.99 616.963 1038.36
663.36 991.963 700.995 938.214 728.726 878.746 745.708 815.366
751.427 750 751.427 -750 745.708 -815.366 728.726 -878.746
700.995 -938.213 663.36 -991.963 616.963 -1038.36 563.214 -1075.99
503.746 -1103.73 440.366 -1120.71 375 -1126.43 -375 -1126.43
-440.366 -1120.71 -503.746 -1103.73 -563.213 -1075.99 -616.963 -1038.36
-663.36 -991.963 -700.995 -938.214 -728.726 -878.746 -745.708 -815.366
-751.427 -750 -751.427 750 -745.708 815.366 -728.726 878.746
-700.995 938.213 -663.36 991.963 -616.963 1038.36 -563.214 1075.99
-503.746 1103.73 -440.366 1120.71 -375 1126.43 375 1126.43
440.366 1120.71))
(shape (polygon B.Cu 0 440.366 1120.71 503.746 1103.73 563.213 1075.99 616.963 1038.36
663.36 991.963 700.995 938.214 728.726 878.746 745.708 815.366
751.427 750 751.427 -750 745.708 -815.366 728.726 -878.746
700.995 -938.213 663.36 -991.963 616.963 -1038.36 563.214 -1075.99
503.746 -1103.73 440.366 -1120.71 375 -1126.43 -375 -1126.43
-440.366 -1120.71 -503.746 -1103.73 -563.213 -1075.99 -616.963 -1038.36
-663.36 -991.963 -700.995 -938.214 -728.726 -878.746 -745.708 -815.366
-751.427 -750 -751.427 750 -745.708 815.366 -728.726 878.746
-700.995 938.213 -663.36 991.963 -616.963 1038.36 -563.214 1075.99
-503.746 1103.73 -440.366 1120.71 -375 1126.43 375 1126.43
440.366 1120.71))
(attach off)
)
(padstack RoundRect[A]Pad_1500x1500_376.427_um
(shape (polygon F.Cu 0 440.366 745.708 503.746 728.726 563.213 700.995 616.963 663.36
663.36 616.963 700.995 563.214 728.726 503.746 745.708 440.366
751.427 375 751.427 -375 745.708 -440.366 728.726 -503.746
700.995 -563.213 663.36 -616.963 616.963 -663.36 563.214 -700.995
503.746 -728.726 440.366 -745.708 375 -751.427 -375 -751.427
-440.366 -745.708 -503.746 -728.726 -563.213 -700.995 -616.963 -663.36
-663.36 -616.963 -700.995 -563.214 -728.726 -503.746 -745.708 -440.366
-751.427 -375 -751.427 375 -745.708 440.366 -728.726 503.746
-700.995 563.213 -663.36 616.963 -616.963 663.36 -563.214 700.995
-503.746 728.726 -440.366 745.708 -375 751.427 375 751.427
440.366 745.708))
(shape (polygon B.Cu 0 440.366 745.708 503.746 728.726 563.213 700.995 616.963 663.36
663.36 616.963 700.995 563.214 728.726 503.746 745.708 440.366
751.427 375 751.427 -375 745.708 -440.366 728.726 -503.746
700.995 -563.213 663.36 -616.963 616.963 -663.36 563.214 -700.995
503.746 -728.726 440.366 -745.708 375 -751.427 -375 -751.427
-440.366 -745.708 -503.746 -728.726 -563.213 -700.995 -616.963 -663.36
-663.36 -616.963 -700.995 -563.214 -728.726 -503.746 -745.708 -440.366
-751.427 -375 -751.427 375 -745.708 440.366 -728.726 503.746
-700.995 563.213 -663.36 616.963 -616.963 663.36 -563.214 700.995
-503.746 728.726 -440.366 745.708 -375 751.427 375 751.427
440.366 745.708))
(attach off)
)
(padstack Rect[B]Pad_2600x2600_um
(shape (rect B.Cu -1300 -1300 1300 1300))
(attach off)
)
(padstack Rect[B]Pad_900x900_um
(shape (rect B.Cu -450 -450 450 450))
(attach off)
)
(padstack Rect[B]Pad_900x1250_um
(shape (rect B.Cu -450 -625 450 625))
(attach off)
)
(padstack Rect[T]Pad_2600x2600_um
(shape (rect F.Cu -1300 -1300 1300 1300))
(attach off)
)
(padstack Rect[T]Pad_900x900_um
(shape (rect F.Cu -450 -450 450 450))
(attach off)
)
(padstack Rect[T]Pad_900x1250_um
(shape (rect F.Cu -450 -625 450 625))
(attach off)
)
(padstack Rect[A]Pad_1752.6x1752.6_um
(shape (rect F.Cu -876.3 -876.3 876.3 876.3))
(shape (rect B.Cu -876.3 -876.3 876.3 876.3))
(attach off)
)
(padstack "Via[0-1]_800:400_um"
(shape (circle F.Cu 800))
(shape (circle B.Cu 800))
(attach off)
)
)
(network
(net P6
(pins S1-1 S1-1@1 S2-1 S2-1@1 MCU1-21)
)
(net GND
(pins S1-2 S1-2@1 S2-2 S2-2@1 S3-2 S3-2@1 S4-2 S4-2@1 S5-2 S5-2@1 S6-2 S6-2@1
S7-2 S7-2@1 S8-2 S8-2@1 S9-2 S9-2@1 S10-2 S10-2@1 S11-2 S11-2@1 S12-2 S12-2@1
S13-2 S13-2@1 S14-2 S14-2@1 S15-2 S15-2@1 S16-2 S16-2@1 S17-2 S17-2@1 S18-2
S18-2@1 S19-2 S19-2@1 S20-2 S20-2@1 S21-2 S21-2@1 S22-2 S22-2@1 S23-2 S23-2@1
S24-2 S24-2@1 S25-2 S25-2@1 S26-2 S26-2@1 S27-2 S27-2@1 S28-2 S28-2@1 S29-2
S29-2@1 S30-2 S30-2@1 S31-2 S31-2@1 S32-2 S32-2@1 S33-2 S33-2@1 S34-2 S34-2@1
S35-2 S35-2@1 S36-2 S36-2@1 MCU1-2 MCU1-15 MCU1-16 B1-2)
)
(net P5
(pins S3-1 S3-1@1 S4-1 S4-1@1 MCU1-20)
)
(net P4
(pins S5-1 S5-1@1 S6-1 S6-1@1 MCU1-19)
)
(net P3
(pins S7-1 S7-1@1 S8-1 S8-1@1 MCU1-18)
)
(net P2
(pins S9-1 S9-1@1 S10-1 S10-1@1 MCU1-17)
)
(net P0
(pins S11-1 S11-1@1 S12-1 S12-1@1 MCU1-14)
)
(net P1
(pins S13-1 S13-1@1 S14-1 S14-1@1 MCU1-13)
)
(net P18
(pins S15-1 S15-1@1 S16-1 S16-1@1 MCU1-8)
)
(net P15
(pins S17-1 S17-1@1 S18-1 S18-1@1 MCU1-9)
)
(net P14
(pins S19-1 S19-1@1 S20-1 S20-1@1 MCU1-10)
)
(net P16
(pins S21-1 S21-1@1 S22-1 S22-1@1 MCU1-11)
)
(net P10
(pins S23-1 S23-1@1 S24-1 S24-1@1 MCU1-12)
)
(net P19
(pins S25-1 S25-1@1 S26-1 S26-1@1 MCU1-7)
)
(net P20
(pins S27-1 S27-1@1 S28-1 S28-1@1 MCU1-6)
)
(net P21
(pins S29-1 S29-1@1 S30-1 S30-1@1 MCU1-5)
)
(net P7
(pins S31-1 S31-1@1 S32-1 S32-1@1 MCU1-22)
)
(net P8
(pins S33-1 S33-1@1 S34-1 S34-1@1 MCU1-23)
)
(net P9
(pins S35-1 S35-1@1 S36-1 S36-1@1 MCU1-24)
)
(net RAW
(pins MCU1-1)
)
(net RST
(pins MCU1-3 B1-1)
)
(net VCC
(pins MCU1-4)
)
(net Bplus
(pins MCU1-25 T1-2 T2-2)
)
(net Bminus
(pins MCU1-25@1 PAD1-1@1)
)
(net Braw
(pins T1-1 T2-1 PAD1-1 PAD1-1@2)
)
(class kicad_default "" P0 P1 P10 P14 P15 P16 P18 P19 P2 P20 P21 P3 P4
P5 P6 P7 P8 P9 RST
(circuit
(use_via Via[0-1]_800:400_um)
)
(rule
(width 250)
(clearance 200.1)
)
)
(class Power Bminus Bplus Braw GND RAW VCC
(circuit
(use_via Via[0-1]_800:400_um)
)
(rule
(width 500)
(clearance 200.1)
)
)
)
(wiring
)
)

2168
output/pcbs/board.kicad_pcb
View file

File diff suppressed because it is too large Load diff

74
output/pcbs/board.kicad_prl
View file

@ -1,74 +0,0 @@
{
"board": {
"active_layer": 31,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "board.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

204
output/pcbs/board.kicad_pro
View file

@ -1,204 +0,0 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.075,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"use_height_for_length_calcs": true
},
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "board.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Power",
"nets": [
"Bminus",
"Bplus",
"Braw",
"GND",
"RAW",
"VCC"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.5,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"label_size_ratio": 0.25,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}

33
output/pcbs/board.pro
View file

@ -1,33 +0,0 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]