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output/gerbers/board/gerbers.zip/gerber/board-CmtUser.gbr

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output/gerbers/board/gerbers.zip/gerber/board-CuTop.gbr

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 G04 #@! TO.N,pinky_top*
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 G04 #@! TO.N,P5*
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 G04 #@! TO.N,ring_bottom*
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 G04 #@! TO.N,P20*
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 G04 #@! TO.N,ring_home*
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 G04 #@! TO.N,ring_top*
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 G04 #@! TO.N,P19*
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 G04 #@! TO.N,middle_home*
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 G04 #@! TO.N,P18*
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 G04 #@! TO.N,index_home*
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 G04 #@! TO.N,index_top*
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 G04 #@! TO.N,P15*
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 G04 #@! TO.N,inner_home*
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 G04 #@! TO.N,inner_top*
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 G04 #@! TO.N,home_thumb*
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 G04 #@! TO.N,GND*
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 G04 #@! TD*
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output/gerbers/board/gerbers.zip/gerber/board-SilkTop.gbr

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-X103610000Y49730000D02*
-X103610000Y16710000D01*
-X103610000Y16710000D02*
-X121390000Y16710000D01*
-X121390000Y16710000D02*
-X121390000Y49730000D01*
-X121390000Y49730000D02*
-X103610000Y49730000D01*
-X106150000Y47190000D02*
-X106150000Y44650000D01*
-X106150000Y47190000D02*
-X103610000Y47190000D01*
 X106150000Y44650000D02*
 X103610000Y44650000D01*
+X106150000Y47190000D02*
+X103610000Y47190000D01*
+X106150000Y47190000D02*
+X106150000Y44650000D01*
+X121390000Y49730000D02*
+X103610000Y49730000D01*
+X121390000Y16710000D02*
+X121390000Y49730000D01*
+X103610000Y16710000D02*
+X121390000Y16710000D01*
+X103610000Y49730000D02*
+X103610000Y16710000D01*
 G04 #@! TD*
 G04 #@! TO.C,MCU1*
 X114247619Y46808095D02*

output/gerbers/board/gerbers.zip/gerber/board.drl

@@ -1,7 +1,7 @@
 M48
-; DRILL file {KiCad 5.1.5+dfsg1-2build2} date Sat Sep 18 17:09:25 2021
+; DRILL file {KiCad 5.1.5+dfsg1-2build2} date Sat Sep 18 18:44:29 2021
 ; FORMAT={-:-/ absolute / metric / decimal}
-; #@! TF.CreationDate,2021-09-18T17:09:25+00:00
+; #@! TF.CreationDate,2021-09-18T18:44:29+00:00
 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.5+dfsg1-2build2
 FMAT,2
 METRIC
@@ -18,22 +18,21 @@ G90
 G05
 T1
 X24.771Y25.18
-X33.148Y49.939
+X35.851Y41.225
-X44.275Y43.509
 X44.275Y41.372
-X46.882Y17.133
+X54.046Y29.432
-X52.68Y51.27
+X61.788Y51.133
 X78.408Y48.012
-X80.275Y36.699
+X78.775Y36.782
-X80.275Y21.012
+X81.0Y21.897
-X88.55Y34.975
+X87.368Y14.246
+X89.048Y36.966
 X92.02Y-1.797
+X97.541Y16.958
 X98.275Y45.664
-X99.9Y17.986
+X100.174Y24.218
-X104.985Y-8.881
+X110.303Y-9.264
-X106.999Y1.914
+X121.164Y-20.809
-X115.478Y-19.444
-X120.357Y-20.545
 T3
 X95.631Y-19.523
 X102.23Y-23.333
@@ -146,8 +145,6 @@ X30.5Y45.9
 X41.5Y45.9
 X84.5Y44.2
 X95.5Y44.2
-X12.5Y0.0
-X23.5Y0.0
 X96.668Y-14.348
 X106.194Y-19.848
 X48.5Y49.3
@@ -158,6 +155,8 @@ X30.5Y28.9
 X41.5Y28.9
 X66.5Y45.9
 X77.5Y45.9
+X12.5Y0.0
+X23.5Y0.0
 X30.5Y11.9
 X41.5Y11.9
 T7
@@ -173,6 +172,10 @@ X67.0Y49.65
 X72.0Y51.85
 X72.0Y51.85
 X77.0Y49.65
+X13.0Y3.75
+X18.0Y5.95
+X18.0Y5.95
+X23.0Y3.75
 X31.0Y15.65
 X36.0Y17.85
 X36.0Y17.85
@@ -221,10 +224,6 @@ X85.0Y47.95
 X90.0Y50.15
 X90.0Y50.15
 X95.0Y47.95
-X13.0Y3.75
-X18.0Y5.95
-X18.0Y5.95
-X23.0Y3.75
 X98.976Y-11.35
 X104.406Y-11.945
 X104.406Y-11.945
@@ -234,6 +233,15 @@ X54.0Y55.25
 X54.0Y55.25
 X59.0Y53.05
 T8
+X90.0Y27.2
+X36.0Y45.9
+X90.0Y44.2
+X101.431Y-17.098
+X54.0Y49.3
+X90.0Y10.2
+X36.0Y28.9
+X72.0Y45.9
+X18.0Y0.0
 X36.0Y11.9
 X72.0Y28.9
 X18.0Y34.0
@@ -243,15 +251,6 @@ X72.0Y11.9
 X54.0Y15.3
 X117.349Y-29.312
 X18.0Y17.0
-X90.0Y27.2
-X36.0Y45.9
-X90.0Y44.2
-X18.0Y0.0
-X101.431Y-17.098
-X54.0Y49.3
-X90.0Y10.2
-X36.0Y28.9
-X72.0Y45.9
 T2
 X109.0Y6.8G85X108.4Y6.8
 G05

output/gerbers/board/gerbers.zip/gerber/board.gbrjob

@@ -7,7 +7,7 @@
       "Application": "Pcbnew",
       "Version":     "5.1.5+dfsg1-2build2"
     },
-    "CreationDate":  "2021-09-18T17:09:25+00:00"
+    "CreationDate":  "2021-09-18T18:44:29+00:00"
   },
   "GeneralSpecs":
   {

output/gerbers/board/gerbers.zip/gerber/drill_report.rpt

@@ -1,5 +1,5 @@
 Drill report for output/routed_pcbs/board.kicad_pcb
-Created on Sat Sep 18 17:09:25 2021
+Created on Sat Sep 18 18:44:29 2021
 
 Copper Layer Stackup:
     =============================================================
@@ -10,12 +10,12 @@ Copper Layer Stackup:
 Drill file 'board.drl' contains
     plated through holes:
     =============================================================
-    T1  0.40mm  0.016"  (17 holes)
+    T1  0.40mm  0.016"  (16 holes)
     T2  0.90mm  0.035"  (8 holes)  (with 8 slots)
     T3  0.99mm  0.039"  (36 holes)
     T4  1.09mm  0.043"  (48 holes)
 
-    Total plated holes count 109
+    Total plated holes count 108
 
 
 Not plated through holes are merged with plated holes

output/pcbs/board.dsn

@@ -133,18 +133,18 @@
   )
   (library
     (image PG1350
-      (outline (path signal 150  -7000 6000  -7000 7000))
-      (outline (path signal 150  -7000 -7000  -6000 -7000))
-      (outline (path signal 150  -6000 7000  -7000 7000))
-      (outline (path signal 150  -7000 -7000  -7000 -6000))
-      (outline (path signal 150  7000 -6000  7000 -7000))
-      (outline (path signal 150  7000 7000  6000 7000))
-      (outline (path signal 150  6000 -7000  7000 -7000))
-      (outline (path signal 150  7000 7000  7000 6000))
-      (outline (path signal 150  -9000 8500  9000 8500))
-      (outline (path signal 150  9000 8500  9000 -8500))
-      (outline (path signal 150  9000 -8500  -9000 -8500))
       (outline (path signal 150  -9000 -8500  -9000 8500))
+      (outline (path signal 150  9000 -8500  -9000 -8500))
+      (outline (path signal 150  9000 8500  9000 -8500))
+      (outline (path signal 150  -9000 8500  9000 8500))
+      (outline (path signal 150  7000 7000  7000 6000))
+      (outline (path signal 150  6000 -7000  7000 -7000))
+      (outline (path signal 150  7000 7000  6000 7000))
+      (outline (path signal 150  7000 -6000  7000 -7000))
+      (outline (path signal 150  -7000 -7000  -7000 -6000))
+      (outline (path signal 150  -6000 7000  -7000 7000))
+      (outline (path signal 150  -7000 -7000  -6000 -7000))
+      (outline (path signal 150  -7000 6000  -7000 7000))
       (pin Rect[B]Pad_2600x2600_um 1 -3275 5950)
       (pin Rect[B]Pad_2600x2600_um 2 8275 3750)
       (pin Rect[T]Pad_2600x2600_um 1@1 3275 5950)
@@ -165,20 +165,20 @@
       (keepout "" (circle B.Cu 3000 0 5950))
     )
     (image ComboDiode
-      (outline (path signal 100  250 0  750 0))
-      (outline (path signal 100  250 -400  -350 0))
-      (outline (path signal 100  250 400  250 -400))
-      (outline (path signal 100  -350 0  250 400))
-      (outline (path signal 100  -350 0  -350 -550))
-      (outline (path signal 100  -350 0  -350 550))
       (outline (path signal 100  -750 0  -350 0))
-      (outline (path signal 100  250 0  750 0))
-      (outline (path signal 100  250 -400  -350 0))
-      (outline (path signal 100  250 400  250 -400))
-      (outline (path signal 100  -350 0  250 400))
-      (outline (path signal 100  -350 0  -350 -550))
       (outline (path signal 100  -350 0  -350 550))
+      (outline (path signal 100  -350 0  -350 -550))
+      (outline (path signal 100  -350 0  250 400))
+      (outline (path signal 100  250 400  250 -400))
+      (outline (path signal 100  250 -400  -350 0))
+      (outline (path signal 100  250 0  750 0))
       (outline (path signal 100  -750 0  -350 0))
+      (outline (path signal 100  -350 0  -350 550))
+      (outline (path signal 100  -350 0  -350 -550))
+      (outline (path signal 100  -350 0  250 400))
+      (outline (path signal 100  250 400  250 -400))
+      (outline (path signal 100  250 -400  -350 0))
+      (outline (path signal 100  250 0  750 0))
       (pin Rect[T]Pad_900x1200_um 1 -1650 0)
       (pin Rect[B]Pad_900x1200_um 2 1650 0)
       (pin Rect[B]Pad_900x1200_um 1@1 -1650 0)
@@ -187,20 +187,20 @@
       (pin Rect[A]Pad_1778x1778_um 2@2 -3810 0)
     )
     (image ComboDiode::1
-      (outline (path signal 100  250 0  750 0))
-      (outline (path signal 100  250 -400  -350 0))
-      (outline (path signal 100  250 400  250 -400))
-      (outline (path signal 100  -350 0  250 400))
-      (outline (path signal 100  -350 0  -350 -550))
-      (outline (path signal 100  -350 0  -350 550))
       (outline (path signal 100  -750 0  -350 0))
-      (outline (path signal 100  250 0  750 0))
-      (outline (path signal 100  250 -400  -350 0))
-      (outline (path signal 100  250 400  250 -400))
-      (outline (path signal 100  -350 0  250 400))
-      (outline (path signal 100  -350 0  -350 -550))
       (outline (path signal 100  -350 0  -350 550))
+      (outline (path signal 100  -350 0  -350 -550))
+      (outline (path signal 100  -350 0  250 400))
+      (outline (path signal 100  250 400  250 -400))
+      (outline (path signal 100  250 -400  -350 0))
+      (outline (path signal 100  250 0  750 0))
       (outline (path signal 100  -750 0  -350 0))
+      (outline (path signal 100  -350 0  -350 550))
+      (outline (path signal 100  -350 0  -350 -550))
+      (outline (path signal 100  -350 0  250 400))
+      (outline (path signal 100  250 400  250 -400))
+      (outline (path signal 100  250 -400  -350 0))
+      (outline (path signal 100  250 0  750 0))
       (pin Rect[T]Pad_900x1200_um 1 -1650 -0.001)
       (pin Rect[B]Pad_900x1200_um 2 1650 0.001)
       (pin Rect[B]Pad_900x1200_um 1@1 -1650 -0.001)
@@ -209,17 +209,17 @@
       (pin Rect[A]Pad_1778x1778_um 2@2 -3810 0.001)
     )
     (image ProMicro
-      (outline (path signal 150  -19304 3810  -14224 3810))
-      (outline (path signal 150  -19304 -3810  -19304 3810))
-      (outline (path signal 150  -14224 -3810  -19304 -3810))
-      (outline (path signal 150  -14224 3810  -14224 -3810))
-      (outline (path signal 150  -17780 -8890  15240 -8890))
-      (outline (path signal 150  15240 -8890  15240 8890))
-      (outline (path signal 150  15240 8890  -17780 8890))
-      (outline (path signal 150  -17780 8890  -17780 -8890))
-      (outline (path signal 150  -15240 6350  -12700 6350))
-      (outline (path signal 150  -15240 6350  -15240 8890))
       (outline (path signal 150  -12700 6350  -12700 8890))
+      (outline (path signal 150  -15240 6350  -15240 8890))
+      (outline (path signal 150  -15240 6350  -12700 6350))
+      (outline (path signal 150  -17780 8890  -17780 -8890))
+      (outline (path signal 150  15240 8890  -17780 8890))
+      (outline (path signal 150  15240 -8890  15240 8890))
+      (outline (path signal 150  -17780 -8890  15240 -8890))
+      (outline (path signal 150  -14224 3810  -14224 -3810))
+      (outline (path signal 150  -14224 -3810  -19304 -3810))
+      (outline (path signal 150  -19304 -3810  -19304 3810))
+      (outline (path signal 150  -19304 3810  -14224 3810))
       (pin Rect[A]Pad_1752.6x1752.6_um 1 -13970 7620)
       (pin Round[A]Pad_1752.6_um (rotate 90) 2 -11430 7620)
       (pin Round[A]Pad_1752.6_um (rotate 90) 3 -8890 7620)
@@ -246,17 +246,17 @@
       (pin Round[A]Pad_1752.6_um (rotate 90) 24 13970 -7620)
     )
     (image ProMicro::1
-      (outline (path signal 150  -19304 3810  -14224 3810))
-      (outline (path signal 150  -19304 -3810  -19304 3810))
-      (outline (path signal 150  -14224 -3810  -19304 -3810))
-      (outline (path signal 150  -14224 3810  -14224 -3810))
-      (outline (path signal 150  -17780 -8890  15240 -8890))
-      (outline (path signal 150  15240 -8890  15240 8890))
-      (outline (path signal 150  15240 8890  -17780 8890))
-      (outline (path signal 150  -17780 8890  -17780 -8890))
-      (outline (path signal 150  -15240 -6350  -12700 -6350))
-      (outline (path signal 150  -15240 -6350  -15240 -8890))
       (outline (path signal 150  -12700 -6350  -12700 -8890))
+      (outline (path signal 150  -15240 -6350  -15240 -8890))
+      (outline (path signal 150  -15240 -6350  -12700 -6350))
+      (outline (path signal 150  -17780 8890  -17780 -8890))
+      (outline (path signal 150  15240 8890  -17780 8890))
+      (outline (path signal 150  15240 -8890  15240 8890))
+      (outline (path signal 150  -17780 -8890  15240 -8890))
+      (outline (path signal 150  -14224 3810  -14224 -3810))
+      (outline (path signal 150  -14224 -3810  -19304 -3810))
+      (outline (path signal 150  -19304 -3810  -19304 3810))
+      (outline (path signal 150  -19304 3810  -14224 3810))
       (pin Rect[A]Pad_1752.6x1752.6_um 1 -13970 -7620)
       (pin Round[A]Pad_1752.6_um (rotate 90) 2 -11430 -7620)
       (pin Round[A]Pad_1752.6_um (rotate 90) 3 -8890 -7620)
@@ -283,13 +283,13 @@
       (pin Round[A]Pad_1752.6_um (rotate 90) 24 13970 7620)
     )
     (image "TRRS-PJ-320A-dual"
-      (outline (path signal 150  500 2000  -5100 2000))
-      (outline (path signal 150  -5100 0  -5100 2000))
-      (outline (path signal 150  500 0  500 2000))
-      (outline (path signal 150  -5350 0  -5350 -12100))
-      (outline (path signal 150  750 0  750 -12100))
-      (outline (path signal 150  750 -12100  -5350 -12100))
       (outline (path signal 150  750 0  -5350 0))
+      (outline (path signal 150  750 -12100  -5350 -12100))
+      (outline (path signal 150  750 0  750 -12100))
+      (outline (path signal 150  -5350 0  -5350 -12100))
+      (outline (path signal 150  500 0  500 2000))
+      (outline (path signal 150  -5100 0  -5100 2000))
+      (outline (path signal 150  500 2000  -5100 2000))
       (pin Oval[A]Pad_1600x2200_um 1 0 -11300)
       (pin Oval[A]Pad_1600x2200_um 2 -4600 -10200)
       (pin Oval[A]Pad_1600x2200_um 3 -4600 -6200)
@@ -475,11 +475,10 @@
     (net P9
       (pins MCU1-24 MCU2-24)
     )
-    (class kicad_default "" GND P0 P1 P10 P14 P15 P16 P18 P19 P2 P20 P21 P3
+    (class kicad_default "" P0 P1 P10 P14 P15 P16 P18 P19 P2 P20 P21 P3 P4
-      P4 P5 P6 P7 P8 P9 RAW RST VCC far_thumb home_thumb index_bottom index_home
+      P5 P6 P7 P8 P9 RST far_thumb home_thumb index_bottom index_home index_top
-      index_top inner_bottom inner_home inner_top middle_bottom middle_home
+      inner_bottom inner_home inner_top middle_bottom middle_home middle_top
-      middle_top near_thumb pinky_bottom pinky_home pinky_top ring_bottom
+      near_thumb pinky_bottom pinky_home pinky_top ring_bottom ring_home ring_top
-      ring_home ring_top
       (circuit
         (use_via Via[0-1]_800:400_um)
       )
@@ -488,6 +487,15 @@
         (clearance 200.1)
       )
     )
+    (class Power GND RAW VCC
+      (circuit
+        (use_via Via[0-1]_800:400_um)
+      )
+      (rule
+        (width 500)
+        (clearance 200.1)
+      )
+    )
   )
   (wiring
   )

output/pcbs/board.kicad_pcb

@@ -134,7 +134,7 @@
 (net 39 "P8")
 (net 40 "P9")
             
-  (net_class Default "This is the default net class."
+  (net_class Default "This is the default net class"
     (clearance 0.2)
     (trace_width 0.25)
     (via_dia 0.8)
@@ -169,10 +169,7 @@
 (add_net "P4")
 (add_net "home_thumb")
 (add_net "far_thumb")
-(add_net "RAW")
-(add_net "GND")
 (add_net "RST")
-(add_net "VCC")
 (add_net "P14")
 (add_net "P16")
 (add_net "P10")
@@ -185,6 +182,19 @@
   )
 
             
+  (net_class Power "This is the power net class"
+    (clearance 0.2)
+    (trace_width 0.5)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net "RAW")
+(add_net "GND")
+(add_net "VCC")
+  )
+
+            
         
       (module PG1350 (layer F.Cu) (tedit 5DD50112)
       (at 18 0 0)

output/pcbs/board.pro

@@ -1,29 +1,10 @@
-update=22/05/2015 07:44:53
+update=2021 September 18, Saturday 19:41:55
 version=1
-last_client=kicad
+last_client=pcbnew
 [general]
 version=1
 RootSch=
 BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
 [cvpcb]
 version=1
 NetIExt=net
@@ -31,3 +12,238 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.25
+ViaDiameter1=0.8
+ViaDrill1=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0.05
+SolderMaskMinWidth=0
+SolderPasteClearance=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=Power
+Clearance=0.2
+TrackWidth=0.5
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25

output/pcbs/bottom_plate.kicad_pcb

@@ -121,7 +121,7 @@
 (net 26 "home_thumb")
 (net 27 "far_thumb")
             
-  (net_class Default "This is the default net class."
+  (net_class Default "This is the default net class"
     (clearance 0.2)
     (trace_width 0.25)
     (via_dia 0.8)
@@ -159,6 +159,17 @@
   )
 
             
+  (net_class Power "This is the power net class"
+    (clearance 0.2)
+    (trace_width 0.5)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    
+  )
+
+            
         
       (module PG1350 (layer F.Cu) (tedit 5DD50112)
       (at 18 0 0)

output/pcbs/fp-info-cache

@@ -0,0 +1 @@
+0

output/pcbs/top_plate.kicad_pcb

@@ -121,7 +121,7 @@
 (net 26 "home_thumb")
 (net 27 "far_thumb")
             
-  (net_class Default "This is the default net class."
+  (net_class Default "This is the default net class"
     (clearance 0.2)
     (trace_width 0.25)
     (via_dia 0.8)
@@ -159,6 +159,17 @@
   )
 
             
+  (net_class Power "This is the power net class"
+    (clearance 0.2)
+    (trace_width 0.5)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    
+  )
+
+            
         
       (module PG1350 (layer F.Cu) (tedit 5DD50112)
       (at 18 0 0)

output/routed_pcbs/board.pro

@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]

output/routed_pcbs/fp-info-cache

@@ -0,0 +1 @@
+0

package.json

@@ -1,6 +1,6 @@
 {
     "scripts": {
-        "gen": "ergogen yamkbd.yaml"
+        "gen": "ergogen samoklava.yaml"
     },
     "dependencies": {
         "ergogen": "github:mrzealot/ergogen"